Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems

We present a fast parallel simulator to evaluate the impact of different error control methods on the performance of networks-on-chip (NoCs). The simulator, implemented with message passing interface (MPI) language to exploit multiprocessor server environments, models characteristics of intellectual property (IP) cores, network interfaces (NIs), and routers. Moreover, different error control schemes can be inserted to the simulator in a plug-and-play manner for evaluation. A highly tunable fault injection feature allows estimation of the latency, throughout and energy consumption of an error control scheme against different fault types, fault injection locations and traffic injections. Case NoC studies are presented to demonstrate how the simulator assists in NoC design space exploration, evaluating the impact of different error control methods on NoC performance, and providing design guidelines for NoCs with error control capabilities.